(a) Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a MOS field effect transistor.
(b) Discussion of the Related Art
Known semiconductor devices have a single source/drain junction structure. Recently, as semiconductor devices become increasingly integrated, channel lengths decrease. A source/drain region having a lightly doped drain (LDD) junction structure is used to reduce undesirable effects caused by decreased channel lengths.
FIGS. 1–7 are sectional views illustrating a method of fabricating a related art MOS field effect transistor. As shown in FIG. 1, a gate insulating film pattern 111 and a gate conductive film pattern 112 are stacked sequentially on a semiconductor substrate 100. It is known to form a typical device isolation field and a well region before the gate insulating film pattern 111 and the gate conductive film pattern 112 are formed.
As shown in FIG. 2, an oxide film 121 is formed to cover the semiconductor substrate 100 and the gate conductive film pattern 112. As shown in FIG. 3, a first ion implantation process is then performed to form a first impurity region 101 by implanting impurity ions into the semiconductor substrate 100 at a low concentration.
Subsequently, an oxide film 122 is formed on the entire surface of the structure. As shown in FIG. 5, a nitride film 123 is then formed on the oxide film 122. As shown in FIG. 6, a gate spacer 126 including an oxide film pattern 124 and a nitride film pattern 125 is next formed on a side wall of the gate conductive film pattern 112 through a typical anisotropic etching process.
As shown in FIG. 7, a second ion implantation process is performed to form a second impurity region 102 by implanting impurity ions into the semiconductor substrate 100 at a high concentration, using the gate spacer 126 as an ion implantation barrier. The first and second impurity regions 101 and 102 form a source/drain region 103 having an LDD structure.
In the method of fabricating the related art MOS field effect transistor, the first and second ion implantation processes should be performed to form the source/drain region 103 having the LDD structure. Particularly, the second ion implantation process should be performed after the gate spacer 126 is formed on the side wall of the gate conductive film pattern 112. When a metal silicide film is formed on the source/drain region 103, the gate spacer 126 is also used to electrically isolate the metal silicide film from the gate conductive film pattern 112.
However, a gap between adjacent gate conductive film patterns 112 is narrowed due to the gate spacer 126. As a result, when the interlayer insulating film is formed, the gap between the adjacent gate conductive film patterns 112 may not be completely filled with the interlayer insulating film, such that voids are generated.
The voids act as cracks and bridges deteriorating reliability of the device through subsequent thermal and contact processes. For example, in a SRAM, which has a low operation voltage and in which leakage current characteristics are critical, a silicide process may not be performed. In this case, the gate spacer 126 is used only as the ion implantation barrier.